Semiconductor device and ic card

ABSTRACT

In an IC card in which an internal circuit is operated by an internal power supply formed from alternate current from outside received by an antenna, the voltage of the internal power supply sometimes changes due to the operation of the internal circuit. Therefore, the voltage controlling circuit of the present invention includes a voltage controlling current source, and when the internal circuit is not operated and the current higher than a predetermined current is detected in the voltage controlling current source, an operating current detector circuit outputs an enable signal. When the internal circuit is operated in response to the enable signal, the current consumed in the internal circuit is subtracted from the current passing through the voltage controlling current source. Consequently, the current change in the entire internal power supply can be prevented, and the output voltage of the internal power supply can be kept constant.

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a semiconductor device. Moreparticularly, the present invention relates to a circuit for detectingwhether or not power for operating a signal processing unit mounted in asemiconductor integrated circuit device for contactless IC card ispresent.

BACKGROUND OF THE INVENTION

The documents cited in this specification are as follows, and thesedocuments are cited based on their document numbers. Document 1:Japanese Patent Application Laid-Open No. 10-207580. The document 1describes a voltage-monitoring type power on reset circuit (for example,FIG. 2) mounted in a contactless IC card which is operated by theoperating voltage formed by rectifying the alternate current (AC)supplied from outside. The signal outputted from this power on resetcircuit is used for the reset of the microcomputer mounted in the ICcard.

The so-called contactless IC card in which a semiconductor integratedcircuit device and an antenna are provided exchanges the informationbetween an interrogator and the semiconductor integrated circuit device,and it is used to achieve various functions such as the transmission ofthe data held by the contactless IC card and the storage of the datatransmitted from the interrogator. The semiconductor integrated circuitdevice mounted in the contactless IC card receives a high frequencysignal supplied from the interrogator by the antenna mounted in thecontactless IC card and rectifies and smoothes the voltage generated atboth ends of the antenna to form an internal voltage necessary for theoperation of the internal circuit. In this case, when excessive power issupplied from the interrogator and the power supply voltage higher thanthe withstand voltage of the devices constituting the internal circuitis supplied, the devices are broken. For its prevention, a controlcircuit for monitoring the power supply voltage level generated insideis provided in many cases so as not to supply the power supply voltagehigher than the withstand voltage of the devices.

Meanwhile, the signal processing circuit mounted in the semiconductorintegrated circuit device in the contactless IC card detects the powersupply voltage level generated as described above, and if the powersupply voltage reaches a level where the signal processing circuitmounted in operates without malfunction, the signal processing circuitis operated and if the power supply voltage does not reaches a levelwhere the signal processing circuit operates without malfunction, thesignal processing circuit is stopped. As an example of this type, thedocument 1 discloses a signal processing circuit which detects the powersupply voltage level and if the power supply voltage is lower than apredetermined voltage level, the signal processing circuit istransitioned to a reset state and stopped and if the power supplyvoltage is higher than the predetermined voltage level, the reset stateis released to operate the signal processing circuit.

Prior to this application, the inventors of the present invention haveexamined the problems caused when the semiconductor integrated circuitdevice provided with the voltage-monitoring type reset circuit accordingto the document 1 is used in the contactless IC card.

FIG. 1 shows the current (I)-voltage (V) characteristics VL examined bythe inventors of the present invention, which are outputted from arectifier circuit in the case where power is supplied in the form ofelectromagnetic wave from the interrogator and the rectifier circuit isconnected to an antenna provided in the contactless IC card. In thiscase, the characteristics VL are represented by the relationalexpression of V=Vo−I·Rout. This means that the voltage at both ends ofthe antenna is changed depending on the current passing through the loadconnected to the output terminal of the rectifier circuit and isequivalent to the voltage source having the output impedance Rout. Vo isthe voltage when it is assumed that no current passes through the load,and the supply voltage V is reduced when current passes through theload. At this time, the slope of the current-voltage characteristics VLis equal to the output impedance Rout.

FIGS. 2A and 2B show an example of an operating waveform in the casewhere the semiconductor integrated circuit device provided with thereset circuit according to the document 1 is connected to theinterrogator and the antenna with the current-voltage characteristics VLshown in FIG. 1. The power on reset circuit exemplified in FIG. 2 of thedocument 1 generates the power on reset signal by comparing the voltagedivided by the voltage divider for dividing a power supply voltage andthe reference voltage from the bandgap reference circuit. By doing so,when the power supply voltage is higher than a predetermined voltagelevel VACT, the reset state of the signal processing circuit is releasedand the signal processing circuit starts to operate.

The reset signal outputted from the reset circuit of the document 1 ischecked at the time T0 in FIG. 2 before the signal processing circuitstarts to operate, and if the power supply voltage is higher than thepredetermined voltage level VACT, the signal processing circuit isoperated between the time T1 and time T2. In FIG. 2, since the powersupply voltage is higher than the predetermined voltage level VACT atthe time T0, the signal processing circuit mounted inside is permittedto operate and the signal processing circuit starts to operate.Therefore, the consumption current when the signal processing circuit isbeing operated is increased by I1 in comparison to that when it is notoperated.

If the output impedance Rout is 0Ω, the change in power supply voltagelevel due to the change in consumption current does not occur, and thesignal processing circuit can be operated by the power supply voltagehigher than the predetermined power supply voltage level VACT. However,when the output impedance Rout is high, the power supply voltage VDDdrops by the product of the change in consumption current and the outputimpedance Rout. Therefore, since the power supply voltage lower than thepredetermined power supply voltage level VACT by the product of thechange in consumption current and the output impedance Rout is suppliedto the signal processing circuit, the signal processing circuit isoperated by the voltage lower than the predetermined power supplyvoltage level. Consequently, there is the possibility that thecharacteristics of the signal processing circuit are changed and themalfunction due to the characteristic degradation occurs.

An object of the present invention is to provide a semiconductorintegrated circuit device having a function to output a reset signal foroperating a signal processing circuit at a predetermined power supplyvoltage even when the current is changed due to the operation of thesignal processing circuit.

SUMMARY OF THE INVENTION

The typical ones of the inventions disclosed in this application will bebriefly described as follows. That is, an IC card in which an internalcircuit is operated by an internal power supply formed in a voltagecontrolling circuit by alternate current from outside received by anantenna is provided, in which the operation of the internal circuit iscontrolled by the operating current detector circuit which detects thesupplied current of the internal power supply. Here, the voltagecontrolling circuit of the present invention includes a voltagecontrolling current source, and when the current higher than apredetermined current I1 flows in the voltage controlling current sourcewhile the internal circuit is not operated, the operating currentdetector circuit outputs an enabling signal. When the internal circuitis operated by receiving the enabling signal, the current I1 consumed inthe internal circuit is subtracted from the current passing through thevoltage controlling current source. As a result, since the change incurrent in the whole internal power supply can be prevented, the outputvoltage of the internal power supply can be kept constant practically.

BRIEF DESCRIPTIONS OF THE DRAWINGS

FIG. 1 is a graph showing the current-voltage characteristics of aninterrogator and an antenna for describing the present invention;

FIGS. 2A and 2B are waveform diagrams for describing the operation of avoltage-monitoring type power on reset circuit;

FIG. 3 is a block diagram showing an embodiment of a contactless IC cardaccording to the present invention;

FIG. 4 is a basic circuit configuration diagram showing an embodiment ofan operating current detector circuit mounted in a semiconductor deviceaccording to the present invention;

FIGS. 5A to 5D are graphs showing the operating waveform of theoperating current detector circuit mounted in a semiconductor deviceaccording to the present invention;

FIG. 6 is a circuit diagram showing an embodiment of a current sourceapplied to the operating current detector circuit mounted in asemiconductor device according to the present invention;

FIG. 7 is a circuit diagram showing another embodiment of the operatingcurrent detector circuit mounted in a semiconductor device according tothe present invention; and

FIG. 8 is a circuit diagram showing another embodiment of the operatingcurrent detector circuit mounted in a semiconductor device according tothe present invention.

DESCRIPTIONS OF THE PREFERRED EMBODIMENTS

Hereinafter, preferred embodiments of a semiconductor device and an ICcard according to the present invention will be described in detail withreference to the accompanying drawings.

(First Embodiment)

FIG. 3 is a block diagram of an embodiment of a semiconductor integratedcircuit device provided with an operating current detector circuitaccording to the present invention and a contactless IC card having thesemiconductor integrated circuit device mounted therein. The signal andpower outputted in the form of electromagnetic wave from an interrogator(not shown) through an antenna are received by an antenna ANTincorporated in an IC card IC_CARD. Typically, the antenna ANT is anantenna coil formed of wound spiral of wire of a printed circuit board.The semiconductor integrated circuit IC is mounted on the printedcircuit board having this antenna ANT formed thereon. This printedcircuit board is molded with resin to form the IC card. Typically, thepresent invention is applied to a contactless IC card which does nothave electrodes for I/O to and from outside on its surface. Of course,it is also possible to apply the present invention to a dual-type ICcard which has a contactless interface and electrodes for I/O.

Though not particularly limited, the semiconductor integrated circuit ICin FIG. 3 is formed on one semiconductor substrate made of, for example,monocrystal silicon by the conventional technique for manufacturing asemiconductor integrated circuit. A rectifier circuit RECT rectifiesalternate current received by the antenna ANT provided in thecontactless IC card, and a smoothing capacitor C1 smoothes the voltagerectified by the rectifier circuit RECT to generate direct power supplyvoltage. The voltage controlling circuit (or voltage controlling means)REG is means for monitoring and controlling power supply voltage levelso as not to supply the power supply voltage higher than withstandvoltage of the devices constituting a circuit connected to the directpower supply voltage. The voltage difference VOUT of the power supplyvoltage VDD-VSS controlled by the REG is supplied as the operating powersupply voltage of an internal circuit MC, a power on reset circuit POR,a current detector circuit PWR, and a communication circuit RX/TX.

The power on reset circuit POR is a power on reset generator circuitwhich monitors the power supply voltage VDD and sometimes generates apower on reset signal SIG2 at power on. The power on reset signal issupplied to a circuit whose internal state needs to reset at power onsuch as a microcomputer MC.

The current detector circuit PWR determines that the current passingthrough the voltage controlling circuit REG is higher than thepredetermined current and outputs the detection signal SIG1. The SIG1 isused to control the operation of the microcomputer MC as an internalcircuit. The internal circuit MC typically includes an interface circuit(I/O) for the communication circuit RX/TX, a central processing unit(CPU), a nonvolatile memory unit composed of a RAM, a flash memory, orEEPROM, and a co-processor. In this case, since the information isencoded in the communication using the IC card with outside, theco-processor is necessary for decoding the encoded received data. Theco-processor consumes relatively large operating current when it startsto operate, which frequently causes the voltage drop. Therefore, in anexample of the present invention, the detection signal SIG1 is used tocontrol the operation of one co-processor in the internal circuit.Usually, the co-processor starts to operate when the operation requestfrom the CPU and the enable condition of the SIG1 are satisfied in theAND condition. The LG1 in the internal circuit MC in FIG. 3 usuallyrepresents a circuit block performing one function, and the co-processoris one of the typical examples thereof in this embodiment.

The interrogator RX/TX includes a receiver and a transmitter. Thereceiver demodulates the information signal superposed in the alternatecurrent received by the antenna ANT provided in the contactless IC cardand supplies the demodulated signal to the internal circuit MC as adigital information signal. The receiver also has a function to generatea clock signal. Meanwhile, the transmitter receives the digitalinformation signal outputted from the internal MC and forms alternatecurrent to be outputted to the outside through an antenna.

FIG. 4 shows a basic circuit configuration of an embodiment of theoperating current detector circuit PWR according to the presentinvention. In FIG. 4, the voltage controlling circuit REG which controlsthe potential difference VOUT between the power supply potential VDD andthe reference potential VSS to be constant is provided between the powersupply potential VDD and the reference potential VSS, and a voltagecomparator circuit VCC which forms detection voltage corresponding tothe change in output voltage VOUT formed by the voltage controllingcurrent source VCCS is provided between the power supply potential VDDand the reference potential VSS. The voltage controlling current sourceVCCS controls the potential difference VOUT by means of the detectionvoltage outputted by the voltage comparator circuit VCC.

The voltage comparator circuit VCC is composed of the circuit describedbelow. More specifically, a voltage divider resistors R01 and R02 areprovided between the power supply potential VDD and the referencepotential VSS. The divided voltage obtained at a connection node N01between the voltage divider resistors R01 and R02 is supplied to thenoninversion input (+) of an operational amplifier circuit A01. Thereference voltage source VREF is connected between an inversion input(−) of the operational amplifier circuit A01 and the reference potentialVSS.

The voltage controlling current source VCCS in FIG. 4 is composed of thecircuit described below. More specifically, an NMOS transistor M01 whosegate terminal is connected to the output terminal of the operationalamplifier circuit A01 is connected between the connection node N02 andthe reference potential VSS. Hereinafter, the NMOS transistor, namely,an n type MOSFET is abbreviated to NMOS, and PMOS transistor, namely, ap type MOSFET is abbreviated to NMOS. In the present invention, the casewhere a typical MOSFET (Metal Oxide Semiconductor Field EffectTransistor) is used as an example will be described. However, it is alsopossible to use the MISFET (Metal Insulator Semiconductor Field EffectTransistor).

The operating current detector circuit PWR is composed of the circuitdescribed below. More specifically, the PMOS transistor M02 whose gateterminal and drain terminal are connected between the power supplypotential VDD and the connection node N2 is connected and the PMOStransistor M03 whose gate terminal is connected to the connection nodeN02 is connected between the power supply potential VDD and theconnection node N03. In this case, the size of the PMOS transistor M03is N times as large as that of the PMOS transistor M02. The M02 and M03form the current mirror circuit, which monitors the current passingthrough the M01 and transfers the current as the drain current of theM03. The reference current source IREF01 is connected between theconnection node N03 and the reference potential VSS, the connection nodeN02 is connected to an input terminal of an inverter INV01 composed ofthe PMOS transistor M04 and the NMOS transistor M05, and an outputterminal of the inverter INV01 is set to the detection signal SIG1 ofFIG. 4. In this case, since the current passing through the PMOStransistor M03 can be reduced by setting the N to a value much smallerthan 1, the error in the current to be detected by the operating currentdetector circuit PWR can be reduced. In addition, the advantage that theconsumption current can be reduced is also achieved. Consequently, it ispreferable that N is set to a value in the range of 0.1 to 0.01.

Note that the operation of the operating current detector circuit PWRcan be understood as follows. That is, when the gate of the M03 in whicha constant current passes by means of the current source IREF01 isinfluenced due to the change in potential of the node N02, the impedanceof the M03 is changed and the voltage of the node N03 is also changed.The potential of the N03 is determined by the inverter INV1 to form theSIG1.

When the voltage level of the output voltage VOUT does not reach thepredetermined voltage, current does not flow through the voltagecontrolling current source VCCS. On the other hand, when the voltagelevel of the output voltage VOUT reaches the predetermined voltage,current flows through the voltage controlling current source VCCS, andthe negative feedback is applied by the output impedance Rout of thepower supply source by the interrogator and the antenna so as to reducethe output voltage VOUT.

The operating current detector circuit PWR which detects the currentproportional to the current passing through the voltage controllingcurrent source VCCS to determine whether or not the current reaches thepredetermined level is provided. When the operating current detectorcircuit PWR determines that the current passing through the voltagecontrolling current source VCCS reaches the predetermined level, itissues the detection signal SIG1.

The detection signal SIG1 of the operating current detector circuit PWRis inputted to the microcomputer MC of FIG. 3, and the operation andnon-operation of the circuit block LG1 is controlled by the detectionsignal SIG1. Therefore, when the output voltage VOUT of the voltagecontrolling current source VCCS reaches a predetermined level andfurther the current passing through the voltage controlling currentsource VCCS reaches a predetermined current, that is, when powernecessary to operate the circuit block LG1 is applied, the detectionsignal SIG1 activates the circuit block LG1.

In this embodiment, when the divided voltage obtained at the connectionnode N01 is higher than the reference voltage VREF, the current startsto flow through the NMOS M01 and the PMOS M02. The negative feedback isapplied by this current and the output impedance Rout so as to reducethe output voltage VOUT.

When the current passing through the NMOS M03 is lower than the currentsource IREF1, the potential at the connection node N03 is equivalent tothe reference potential VSS, and “H” is outputted to the detectionsignal SIG1 of the inverter INV01. The current passing through the NMOSM03 is higher than the current source IREF01, the potential at theconnection node N03 is equivalent to the reference potential VSS, and“L” is outputted to the detection signal SIG1 of the inverter INV01. Atthis time, the current passing through the NMOS M01 is 1/N times as highas that of the current source IREF1. In this case, the current 1/N timesas high as that of the current source IREF1 is set to be higher than theconsumption current I1 of the circuit block LG1 activated by thedetection signal SIG1.

When the detection signal SIG1 is “H”, the circuit block LG1 is stopped.When the detection signal SIG1 is “L”, the LG1 is operated. When the LG1is operated, the consumption current is increased and the output voltageVOUT is decreased due to the output impedance Rout. However, the currentpassing through the NMOS M01 is reduced by the negative feedback and theoutput voltage VOUT is controlled to be a predetermined voltage.

FIGS. 5A to 5D show an example of the operating waveforms in the casewhere the semiconductor integrated circuit device in FIG. 3 providedwith the operating current detector circuit in FIG. 4 is connected tothe interrogator and the antenna having the current-voltagecharacteristics shown in FIG. 1. FIG. 5A shows the change with time ofthe alternate waveform inputted to the antenna ANT, FIG. 5B shows thechange with time of the output voltage VOUT, FIG. 5C shows the changewith time of the current ILG1 passing through the circuit block(co-processor) LG1, and FIG. 5D shows the change with time of thecurrent IVCCS passing through the voltage controlling circuit VCCS (moreconcretely, M01). Note that, in the alternate waveform in FIG. 5A, thedigital signal which is phase-modulated by the sine wave is superposed.This sine wave typically has the frequency of about 13.56 MHz, and thetime axis is magnified in these drawings.

The detection signal SIG1 outputted from the operating current detectorcircuit shown in FIG. 4 is checked at the time T0 before the circuitblock LG1 starts to operate, and when a predetermined current passesthrough the voltage controlling current source VCCS, the LG1 is operatedfrom the time T1 to T2. At this time, if the output voltage VOUT reachesa predetermined voltage level and further the current higher than theoperating current I1 flows in the voltage controlling current sourceVCCS, the operation of the signal processing circuit mounted inside ispermitted and the signal processing circuit is operated from the time T1to T2.

By doing so, the circuit block LG1 is activated and the operatingcurrent I1 of the LG1 starts to flow. The output voltage VOUT isdecreased due to the output impedance Rout. However, the current passingthrough the voltage controlling circuit is reduced only by the operatingcurrent I1 by the negative feedback so as to control the output voltageVOUT to be a predetermined voltage. Therefore, when the signalprocessing circuit LG1 is operated, the output voltage VOUT is keptconstant at any time, and even when the consumption current is changeddue to the operation of the LG1, a signal processing circuit can beoperated at a predetermined power supply voltage level. Morespecifically, the voltage controlling circuit REG according to thepresent invention is configured such that the current higher than thecurrent I1 flows through the M01 of the voltage controlling currentsource VCCS when the LG1 is not operated and the current I1 consumed inthe LG1 is decreased from the current passing through the VCCS when theLG1 is operated. By doing so, the current change in the entire circuitcan be prevented and as a result, the output voltage VOUT can be keptconstant.

FIG. 6 shows an example of a reference current source IREF01. In FIG. 6,a current-mirror type reference current source is used. The NMOS M31which is diode-connected and the resistor R31 are connected in seriesbetween VDD and VSS to form a reference current circuit and the NMOS M32connected by means of a current-mirror connection is used as the currentsource and is connected at the connection node N03. Also, the resistorconnected between VSS and N03 can be used as a simpler modificationexample of the reference current source IREF01.

(Second Embodiment)

FIG. 7 is a circuit diagram showing another embodiment of the voltagecontrolling circuit REG and the operating current detector circuit PWRin FIG. 4. The voltage comparator circuit VCC in FIG. 7 has the sameconfiguration as that in FIG. 4. Meanwhile, the voltage controllingcurrent source VCCS differs in that the drain of the NMOS M11 isdirectly connected to VDD.

The operating current detector circuit PWR in FIG. 7 is composed of thecircuit described below. More specifically, the NMOS M12 whose gateterminal is connected to the output terminal of the operationalamplifier circuit All is connected between the connection node N12 andthe reference potential VSS. In this case, the size of the NMOS M12 is Ntimes as large as that of the NMOS transistor M11. The reference currentsource IREF11 is connected between the power supply potential VDD andthe connection node N12, the connection node 12 is connected to theinput terminal of the inverter INV11, and the output terminal of theinverter INV11 is set to the detection signal SIG1 in FIG. 4.

The reference current source IREF11 in FIG. 7 can be obtained in thecircuit in which VDD and VSS in the circuit of FIG. 6 are inverted so asto change M31 and M32 into the PMOS. Also, the resistor can be used as asimpler example of the reference current source IREF11.

In this embodiment, when the divided voltage obtained at the connectionnode N11 is higher than the reference voltage VREF, the current startsto flow through the NMOS M11. The negative feedback is applied by thiscurrent and the output impedance Rout so as to reduce the output voltageVOUT. Since the size of the NMOS M12 is N times as large as that of theNMOS M11, the current passing through the NMOS M12 is N times as high asthat passing through the NMOS M11.

When the current passing through the NMOS M12 is lower than the currentsource IREF11, the potential at the connection node N12 is equivalent tothe power supply potential VDD, and “L” is outputted to the detectionsignal of the inverter INV11. When the current passing through the NMOSM12 is higher than the current source IREF11, the potential at theconnection node N12 is equivalent to the reference potential VSS, and“H” is outputted to the detection signal SIG1 of the inverter INV11. Atthis time, the current passing through the NMOS M11 is 1/N times as highas the current source IREF1. In this case, the consumption current ofthe circuit block LG1 activated by the detection signal SIG1 is set tobe lower than the current 1/N times as high as that of the currentsource IREF1.

The circuit block LG1 is controlled by the detection signal SIG1 in thesame way as that shown in FIG. 4. Therefore, the circuit in thisembodiment shown in FIG. 7 can acquire the same function as that in theembodiment shown in FIG. 4, and further, it is possible to reduce thearea used by the transistor.

(Third Embodiment)

FIG. 8 is a circuit diagram showing another embodiment of the operatingcurrent detector circuit PWR mounted in a semiconductor integratedcircuit device according to the present invention. In this embodiment, amodification example of the operating current detector circuit PWR shownin FIG. 7 is described.

The operating current detector circuit PWR in FIG. 8 is composed of acircuit described below. That is, the NMOS M21 whose gate terminal isconnected to the output terminal of the operational amplifier circuitA21 is connected between the connection node N21 and the referencepotential VSS. The reference current source IREF 21 is connected betweenthe power supply potential VDD and the connection node N21, an inputterminal of the low pass filter LPF composed of the resistor R21 and thecapacitor C11 is connected to the connection node N21, the PMOS M22whose gate terminal is connected to the output terminal of the low passfilter LPF is connected between the power supply potential VDD and theconnection node N22, the reference current source IREF22 is connectedbetween the connection node N22 and the reference potential VSS, theconnection node N22 is connected to the input terminal of the inverterINV21, and the output terminal of the inverter INV21 is set to thedetection signal SIG1 in FIG. 6. In this case, the low pass filter isused to remove the high-frequency component of the connection node N22,and any circuit configuration can be available for the low pass filter.

The reference current source IREF21 in FIG. 8 can be obtained in thecircuit in which VDD and VSS in the circuit of FIG. 6 are inverted so asto change M31 and M32 into the PMOS. Also, the reference current sourceIREF22 can be obtained by the same circuit shown in FIG. 6. The resistorcan be used as a simpler example of the IREF21 and IREF22.

In this embodiment, when the current passing through the NMOS M21 islower than the current source IREF21, the potential at the connectionnode N21 is equivalent to the power supply potential VDD and “H” isoutputted to the detection signal SIG1 of the inverter INV21. When thecurrent passing through the NMOS M21 is higher than the current sourceIREF21, the potential at the connection node N21 is equivalent to thereference potential VSS and “L” is outputted to the detection signalSIG1 of the inverter INV21. At this time, the current passing throughthe NMOS N11 is 1/N times as high as the current source IREF21.

The circuit block LG1 is controlled by the detection signal SIG1 in thesame way as that shown in FIG. 4. Therefore, the circuit in thisembodiment shown in FIG. 8 can acquire the same function as that in theembodiment shown in FIG. 4, and further, it is possible to reduce thepass current of the detector circuit.

In the foregoing, the invention made by the inventors of the presentinvention has been concretely described based on the embodiments.However, it is needless to say that the present invention is not limitedto the foregoing embodiments and various modifications and alterationscan be made within the scope of the present invention. For example, itis possible to apply the detection signal SIG1 of the operating currentdetector circuit to the output signal of the power on reset circuit PORshown in FIG. 3, and it is also possible to provide a plurality ofoperating current detector circuits each having different current valuesto be detected for a plurality of signal processing circuits havingdifferent operating currents. In this case, the reference voltagepassing through the voltage controlling current source can be adjustedin accordance with the target circuit. Also, the case of thesemiconductor integrated circuit device mounted in the contactless ICcard has been described above. However, the same effects can be achievedalso in another semiconductor integrated circuit device having a voltagecontrolling circuit mounted therein by detecting the operation state ofthe voltage controlling circuit mounted therein.

The effects achieved by the present invention are as follows. That is,by permitting the operation of the internal signal processing circuitwhen it is determined that current passing through an internal voltagecontrolling circuit reaches a predetermined current, the signalprocessing circuit can be operated at a predetermined power supplyvoltage even when the current is changed due to the operation of thesignal processing circuit. Consequently, it becomes possible to providea signal processing circuit with a narrow power supply voltage rangewhich can operate without malfunction, and thus, it is possible toreduce the characteristic change due to the change of the power supplyvoltage level and the malfunction due to the characteristic degradation.

The present invention can be preferably applied to an IC card and thelike.

1. An IC card, comprising: an antenna for receiving alternate currentsuperposed with an information signal; a rectifier circuit for receivingthe alternate current received by said antenna and outputting rectifiervoltage to obtain direct power supply; a voltage controlling circuit forreceiving the rectifier voltage outputted from said rectifier circuitand outputting operating voltage which is voltage difference between afirst potential and a second potential; an internal circuit to whichsaid operating voltage is supplied; and an operating current detectorcircuit for detecting current supplied by said operating voltage andoutputting a detection signal indicating whether or not the current ishigher than a predetermined current value, wherein anoperation/non-operation of said internal circuit is controlled by saiddetection signal.
 2. The IC card according to claim 1, wherein saidvoltage controlling circuit includes: a voltage comparator circuit whichcompares said operating voltage and a predetermined reference voltage;and a voltage controlling current source controlled by an output of saidvoltage comparator circuit, and said operating current detector circuitdetects current passing through said voltage controlling current sourceand outputs said detection signal.
 3. The IC card according to claim 2,wherein said voltage controlling circuit controls a voltage value ofsaid operating voltage by subtracting the current supplied to theinternal circuit from the current passing through said voltagecontrolling current source when said detection signal is named enableand said internal circuit starts to operate.
 4. The IC card according toclaim 1, wherein said internal circuit described in claim 1 has acentral processing unit (CPU) and a co-processor, and said co-processorcan operate when said detection signal is named enable.
 5. The IC cardaccording to claim 1, further comprising: a communication circuitincluding a receiver for demodulating the information signal superposedin the alternate current received from said antenna to output the signalas a digital information signal to said internal circuit and atransmitter for receiving digital information signal outputted from saidinternal circuit to form alternate current to be outputted from saidantenna to outside.
 6. The IC card according to claim 1, furthercomprising: a power on reset circuit for monitoring the voltage value ofsaid operating voltage and outputting a reset signal, wherein saidinternal circuit includes a central processing unit (CPU) and aco-processor, said central processing unit starts to operate when saidreset signal is named enable, and said co-processor is permitted tooperate when said detection signal is named enable.
 7. The IC cardaccording to claim 1, wherein said rectifier circuit, said voltagecontrolling circuit, said internal circuit, and said operating currentdetector circuit are formed as a monolithic semiconductor integratedcircuit on a silicon substrate, and said semiconductor integratedcircuit is mounted on a wiring circuit board on which said antenna isformed as an antenna coil by a wiring pattern and these are sealed withresin.
 8. The IC card according to claim 2, wherein said voltagecomparator circuit includes an operational amplifier for dividing saidoperating voltage to compare with said reference voltage, said voltagecontrolling current source includes a first MISFET whose gate iscontrolled by the output of said operational amplifier, said operatingcurrent detector circuit includes a first current source connected inseries to a second MISFET between said first potential and said secondpotential, said operating current detector circuit detects a change inpotential at a connection node between said first current source andsaid second MISFET to form said detection signal when the impedance ofsaid second MISFET changes in response to the current passing throughsaid first MISFET.
 9. The IC card according to claim 8, wherein gatepotential of said second MISFET is controlled in accordance with thecurrent passing through said first MISFET.
 10. A semiconductor device,comprising: a rectifier circuit for receiving alternate current suppliedfrom outside and outputting rectifier voltage to obtain direct powersupply; a voltage controlling circuit for receiving said rectifiervoltage and outputting operating voltage which is voltage differencebetween a first potential and a second potential; an internal circuit towhich said operating voltage is supplied; and an operating currentdetector circuit for detecting current supplied by said operatingvoltage and outputting a detection signal indicating whether or not thecurrent is higher than a predetermined current value, wherein anoperation/non-operation of said internal circuit is controlled by saiddetection signal.
 11. The semiconductor device according to claim 10,wherein said voltage controlling circuit includes a voltage comparatorcircuit for comparing said operating voltage and a predeterminedreference voltage and a voltage controlling current source controlled byan output of said voltage comparator circuit, and said operating currentdetector circuit detects current passing through said voltagecontrolling current source and outputs said detection signal.
 12. Thesemiconductor device according to claim 11, wherein the voltagecomparator circuit includes an operational amplifier for dividing saidoperating voltage to compare with said reference voltage, said voltagecontrolling current source includes a first MISFET whose gate iscontrolled by the output of said operational amplifier, said operatingcurrent detector circuit includes a current mirror circuit fortransferring current passing through said first MISFET as source/draincurrent of a second MISFET and a first current source connected inseries to the second MISFET of said current mirror circuit between saidfirst potential and said second potential, and said operating currentdetector circuit detects a change in potential at a connection nodebetween said first current source and said second MISFET to form saiddetection signal when the current passing through said second MISFETchanges in response to the current passing through said first MISFET.13. The semiconductor device according to claim 12, wherein said voltagecontrolling circuit controls a voltage value of said operating voltageby subtracting the current supplied to the internal circuit from thecurrent passing through said first MISFET when said detection signal isnamed enable and said internal circuit starts to operate.
 14. Thesemiconductor device according to claim 12, wherein the voltagecomparator circuit includes an operational amplifier for dividing saidoperating voltage to compare with said reference voltage, said voltagecontrolling current source includes a third MISFET whose source anddrain are connected between said first potential and said secondpotential and whose gate is controlled by the output of said operationalamplifier, said operating current detector circuit includes a secondcurrent source and a fourth MISFET connected in series between saidfirst potential and said second potential, and said operating currentdetector circuit detects a change in potential at a connection nodebetween said first current source and said second MISFET and forms saidfirst current source and said fourth MISFET to form said detectionsignal when the gate of said fourth MISFET is controlled by the outputof said operational amplifier.
 15. The semiconductor device according toclaim 12, wherein the voltage comparator circuit includes an operationalamplifier for dividing said operating voltage to compare with saidreference voltage, said voltage controlling current source includes afifth MISFET whose source and drain are connected between said firstpotential and said second potential and whose gate is controlled by theoutput of said operational amplifier, said operating current detectorcircuit includes a third current source and a sixth MISFET connected inseries between said first potential and said second potential, a fourthcurrent source and a seventh MISFET connected in series between saidfirst potential and said second potential, and a low pass filterconnected between a connection node between said third current sourceand said sixth MISFET and a gate of said seventh MISFET, and saidoperating current detector circuit detects a change in potential at aconnection node between said fourth current source and said seventhMISFET to form said detection signal when the gate of said fourth MISFETis controlled by an output of said operational amplifier.
 16. Asemiconductor device, comprising: a rectifier circuit for receivingalternate current supplied from outside and outputting rectifier voltageto obtain direct power supply; a voltage controlling circuit forreceiving said rectifier voltage and outputting operating voltage whichis voltage difference between a first potential and a second potential;and an internal circuit to which said operating voltage is supplied,.wherein said voltage controlling circuit includes a voltage controllingcurrent source, allows said internal circuit to operate when currentpassing through said voltage controlling current source is higher than apredetermined value, and controls said operating voltage by subtractingthe current supplied to said internal circuit from the current passingthrough said voltage controlling current source when said internalcircuit starts to operate.